1. Field of the Invention
The present invention relates generally to a process for flip chip connecting a semiconductor chip.
2. Description of the Related Art
According to the progress of information processing technology, semiconductor devices that form the major part of information processing equipment have an ever increasing demand for greater capacity. Nowadays, LSI and VLSI have been put into practical use.
As is well known, these integrated circuit elements have a large number of unit transistors arranged in a matrix form array on a semiconductor chip in a size of several mm.sup.2. When a circuit connection is effected by a wire bonding, the back side of the semiconductor chip is initially bonded on a circuit board by an eutectic alloy or solder or an adhesive. Then, a plurality of electrode terminals (pads) provided on the circumference of the chip are wire bonded with a plurality of electrode terminals (pads) provided on the circuit board for establishing electrical connection with conductors on the circuit board.
However, due to extremely high density, such wire bonding method is not applicable for a large capacity element, such as an LSI. For large capacity elements, it is typical to employ a flip chip connection method, in which solder bumps are arranged in matrix form on a surface side of the semiconductor chip. Upon being mounted on the circuit board, the surface side of the semiconductor chip is mated with the surface of the circuit board so that the solder bumps on the semiconductor chip come into contact with solder bumps on the circuit board and are soldered to each other.
Employing this method, since the semiconductor elements can be directly mounted on the circuit board, signal transmission paths can be significantly shortened This contributes to the reduction of transmission loss of the signal transmitted through the signal transmission paths. In practice, solder bumps having configurations identical to those of the solder bumps on the semiconductor elements are formed on the circuit board, such as those made of ceramic, at positions exactly corresponding to those on the semiconductor elements. The semiconductor element is mounted on the circuit board by mating respective solder bumps thereof with the solder bumps on the circuit board. Thereafter, a heat higher than the melting point of the bumps is applied so as to melt the solder bumps for welding respectively mating bumps.
Most of the current semiconductor integrated circuits are formed of silicon (Si). On the other hand, most of the currently available circuit boards are formed of alumina ceramics or glass ceramics.
As set forth above, large capacity elements, such as LSI, VLSI and so forth are frequently mounted on the circuit board by flip chip connection.
The inventors have proposed in Japanese Patent Application No. 2-118388, which has been commonly assigned to the assignee of the present invention, a method for forming a plurality of solder bumps on the semiconductor chip or the circuit board with high positioning precision. The disclosure of the above-identified Japanese Patent Application is incorporated herein by reference.
Using the solder bumps formed by the proposed method, flip chip connections can be effected in a practical and efficient manner.
A brief discussion of the conventional method will be provided.
At first, as shown in FIG. 2, a metal mask is fitted on a transparent substrate 1 that has high thermal resistance but cannot be connected by soldering, such as a glass plate or a transparent quartz plate. At this position, solder is deposited by vacuum disposition to form solder projections 2 (FIG. 2A).
On the other hand, a substrate 3, such as a semiconductor chip or a circuit board to be processed, is preliminarily formed with pads of gold (Au) or so forth, equal in size to solder bumps formed at positions forming the solder bumps, by way of vacuum desposition or other suitable methods.
The substrate 3 to be processed is heated at a temperature higher than or equal to a melting point of the solder. The solder projections 2 on the transparent substrate 1 are then positioned and aligned with respective corresponding pads 4 arranged in matrix form, and the solder projections 2 and the pads 4 are mated with each other (FIG. 2B).
Since the solder forming the solder projections 2 have low adhering ability to the transparent substrate 1 and have high adhering ability to the pads 4, the solder projections 2 are transferred to the pads 4 to form the solder bumps 5 (FIG. 2C).
A feature of this forming method is that, even when a slight offset is present between the pads 4 on the substrate 3 to be processed and the solder projection 2 on the transparent substrate 1, the semisphere solder bumps 5 can be formed on the pads by self alignment.
Next, the solder bumps 5 thus formed on the semiconductor chip 6 are positioned in alignment with the corresponding solder bumps 5 on the circuit board 7 and then mated with the latter (FIG. 2D). By heating the circuit board 7 to a temperature higher than or equal to the melting point of the solder, the mating solder bumps 5 are molten and are welded to each other. The welded solder is cask-shaped (FIG. 2E).
However, in such a connection method, stress due to the difference in thermal expansion coefficients between the semiconductor chip 6 and the circuit board 7 can concentrate at the junction between the soldered cask form solder and the substrates and thereby lower reliability.
To avoid this problem, various methods of forming the solder mass into a configuration with an intermediate waist portion such that the diameter is reduced have been proposed.
In one of the proposed methods, a plurality of spacers are mounted on the circuit board so as to provide a clearance between the semiconductor chip and circuit board.
However, this method encounters a problem in that it is difficult to maintain sufficient space to insert the spacers because of the small area of the semiconductor chip. Also, it is difficult to maintain the height of the spacers constant. In view of the above, this method is not practical and results in low workability.
Also, there has been proposed another method, in which the semiconductor chip is drawn up after connection to form the waist portion. However, this method is not practical and it lowers the reliability of the products.
Further, Japanese Unexamined Patent Publication (Kokai) No. 4-22130 discloses a flip chip connection method in which stud bumps are formed on a semiconductor chip, on which solder bumps are formed on the periphery of the chip. However, this reference does not disclose the provision of solder bumps on the substrate on which the chip is mounted, in addition to the provision of the solder bumps on the chip. Also, this reference does not disclose the removal of the stud bumps after completion of the flip chip connection.